1. Field of the Invention
This invention relates in general to a ball grid array (xe2x80x9cBGAxe2x80x9d) assembly, and more particularly to a process and assembly for reducing ball grid array (xe2x80x9cBGAxe2x80x9d) warpage caused by the encapsulation step of an attached semiconductor chip mounted to a substrate.
2. Description of the Related Art
In response to current demands from the electronics industry to produce smaller, faster, and more reliable devices, many semiconductor manufactures have looked at exploiting the advantages of ball grid array (xe2x80x9cBGAxe2x80x9d) technology. There are three major types of BGA assemblies in use today, primarily differentiated by the substrate type: tape ball grid array (xe2x80x9cTBGAxe2x80x9d), plastic or laminate ball grid array (xe2x80x9cPBGAxe2x80x9d) and ceramic ball grid array (xe2x80x9cCBGAxe2x80x9d). Each BGA assembly can reduce the required real estate on a card by replacing conventional 304-leaded Quad Flat Packs (xe2x80x9cQFPxe2x80x9d) with a BGA assembly, e.g., 255 I/O CBGA package. Along with the size reduction, the package change allows for an increased connection spacing from 0.020xe2x80x3 to 0.050xe2x80x3, which is very significant for the surface mount attach process.
FIG. 1 illustrates a cross-sectional view of a conventional BGA assembly 9A before a final encapsulation step. FIGS. 2A and 2B illustrate a top plan view and a cross-sectional view of FIG. 1 after the final encapsulation step. More specifically, these figures show a BGA assembly 9A, 9B manufactured by mounting the semiconductor chip 11 on a desired BGA substrate 15, of a type described above. Once mounted, the contact wires 17 are connected between the chip contact terminals 11A and the substrate contact terminals 15A. Next, an array of solder bumps 19 are attached to the bottom surface of the substrate 15 to establish a connection with the contact wires 17 through the substrate 15.
FIGS. 2A and 2B show the final step for completing BGA assembly 9B. In particular, a protective layer 13, of a material such as an epoxy resin, is deposited to encapsulate the chip 11, the contact wires 17, and a portion of the substrate 15. However, when the encapsulation layer 13 cures, it also shrinks to warp the resultant BGA assembly 9B. This warpage during the encapsulation process is due to the different coefficient of thermal expansion (xe2x80x9cCTExe2x80x9d) properties between the encapsulating layer 13 and the substrate 15.
If a tested BGA assembly shows signs of warpage, during or after the encapsulation process, it may fail and be scrapped because these types of failures can effect the operation of the resultant assembly. Consequently, process control is the key to high-reliability BGA assemblies.
Currently, the most commonly used process control technique to reduce BGA assembly warpage is encapsulant formulation. However, when an encapsulant formulation technique is used other properties such as processability, reliability, and cost may be sacrificed.
To reduce sacrificing the above properties, the manufacturing process for a BGA assembly is evaluated by inspecting the area array connections. The BGA""s area array connections are on the bottom side of the package, and thus, visibility to the solder joints is only possible through X-ray. This technique only increases the reliability of the manufacturing process after a problem is found. Therefore, it is imperative that the best process for each particular BGA assembly having an encapsulant formulation be identified and verified prior to any attempt at high-volume manufacturing. In turn, once characterized, these processes must be held constant through the proper selection of equipment and operators to ensure repeatability and high throughput yields. Consequently, the process for manufacturing a BGA assembly having an encapsulation formulation to reduce warpage is not only difficult to effectively and efficiently replicate, but also very costly.
In summary, a warped BGA assembly can be a great reliability concern. If the warpage is reduced then the reliability and processability (i.e., trimming or routing, testing, and board mounting) of a BGA assembly is improved. Currently, conventional process steps for reducing BGA warpage are very costly and complicated. Consequently, it would be advantageous to develop a BGA assembly and process of manufacturing that is not only cost effective, but also reliable, easy to implement, and will ultimately reduce encapsulation warpage.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a ball grid array (xe2x80x9cBGAxe2x80x9d) assembly provides a substrate coupled between a semiconductor chip and a BGA structure. A stabilizing plate is coupled to the substrate adjacent the BGA structure, and a protective layer is bonded to and over a portion of the substrate adjacent the semiconductor chip.
In another aspect of the instant invention, a method is provided for manufacturing a semiconductor device assembly. The process includes securing a semiconductor chip to a substrate; coupling a BGA structure to the substrate on an opposite surface of the chip; attaching a stabilizing plate to the substrate adjacent the BGA structure; and encapsulating the chip and a portion of the substrate adjacent the chip.